טכניון מכון טכנולוגי לישראל
הטכניון מכון טכנולוגי לישראל - בית הספר ללימודי מוסמכים  
M.Sc Thesis
M.Sc StudentLevy Yifat
SubjectDigital Circuits Design Using Memristors
DepartmentDepartment of Electrical Engineering
Supervisors Professor Emeritus Avinoam Kolodny
Professor Aby Friedman
Full Thesis textFull thesis text - English Version


Abstract

In the last five decades most of the improvement in computer capabilities has been connected to CMOS scaling. During this period, computer architecture, von Neumann architecture, has not changed. This architecture, in which the memory and the execution unite are separate, requires a large bandwidth for data transfer between the memory and the CPU. The data transfer is both a power and performance bottleneck. New application demands continued scaling in order to get more memory with faster access in less area. It is becoming harder to support new emerging applications and technologies with today’s memory technology and architecture.

Integrating the processor operations or some of them, into the memory can overcome these obstacles and opens up opportunities for novel computer architectures. This kind of architecture can reduce energy requirements and increase performance. The suggested solution is possible, due to new emerging devices, such as memristors, which can store data and perform logic operations in the same unit. These cells are useful for dense integration of logical operations inside a memory array and can also be integrated with CMOS devices.

This thesis proposes a non-volatile memory array that can execute logical operations, including bit sorting, using memristors. The architecture is based on a rectangular logic array structure proposed by Sheldon Akers in the '70s. The proposed memory array is a modified Akers logic array - "A Memristive Akers Array." The array has two configurations or operation modes: storing data and calculation. The stored data in this array is also the input for the logical operation. This research defines and demonstrates, by simulations, the possible operation modes, different logical operations in the array and describes the challenges of this architecture.