טכניון מכון טכנולוגי לישראל
הטכניון מכון טכנולוגי לישראל - בית הספר ללימודי מוסמכים  
M.Sc Thesis
M.Sc StudentZe'ev Rogachevsky
SubjectVLSI Based Carbon Nanotubes
DepartmentDepartment of Electrical Engineering
Supervisor Dr. Yaish Yuval
Full Thesis textFull thesis text - English Version


Abstract

Since the discovery of carbon Nanotubes (CNTs) in 1991 by Sumio Iijima they have been of great interest to the chip industry and researchers. However, two major drawbacks in using CNTs for VLSI (very large scale integration) applications were the difficulty in positioning or growing them at specific known locations and the ability to produce P and N type transistors along the same CNT since the as-prepared CNTs invariably show P-type characteristics.

In this work I will present a simple, quick and non-invasive way to map all the nanotubes on a chip using optical imaging and tiny nanocrystals. After the imaging stage is done, these molecules can be removed leaving no residues and keeping the electrical and mechanical properties of the CNTs as were before.

A new technique was developed to convert P-type CNT transistors to N-type and logic gates were built on the same CNT, functioning in ambient conditions and preserving stable electrical characteristics over more than a few months of use.  

As a final step, I'll present a developed image processing technique and pattern design tool that could automatically design the fabrication pattern of simple components, paving another step to the big dream of the future CNT based VLSI industry.