טכניון מכון טכנולוגי לישראל
הטכניון מכון טכנולוגי לישראל - בית הספר ללימודי מוסמכים  
M.Sc Thesis
M.Sc StudentMarat Radan
SubjectTapping into the Router's Unutilized Processing
Power
DepartmentDepartment of Electrical Engineering
Supervisor Full Professor Keslassy Isaac
Full Thesis textFull thesis text - English Version


Abstract

The Internet has become a central part of modern life, both socially and professionally. Many engineering challenges arise as the Internet's worldwide availability and bandwidth demands increase: The surge in video streaming stresses the bandwidth of the network while often simultaneously requiring latency and jitter guarantees. Social and business networks need to scale to hundreds of millions of users while maintaining privacy, security and quality of service guarantees. These difficult challenges are often addressed by the routers, which are designed to be programmable to accommodate the fast-changing network-bandwidth and service requirements. The growing demand for network programmability has led to the introduction of complex packet processing features that are increasingly hard to provide at full line rates.


Large high-bandwidth routers consist of linecards interconnected by a switch fabric. The processing of packets is performed at the linecards. The most basic and fundamental function of a router is to forward data packets, a relatively simple operation turned complex due to the high arrival rate of packets. Other router applications related to security, encryption or video streaming can require up to two orders of magnitude higher computational complexity than simple packet forwarding. Future applications are expected to run on higher-bandwidth routers and at an even greater computational complexity.


In this research, we introduce a novel load-balancing approach that provides more processing power to congested linecards by tapping into the processing power of underutilized linecards. We define different switch-fabric models, and develop algorithms that aim at minimizing the total average delay and maximizing the capacity region. Using real-life traces and more accurate switch-fabric models, we confirm that our algorithms outperform current algorithms as well as simple alternative load-balancing algorithms. We show that our algorithms are able to increase the utilization and overall performance of the router for common scenarios. In addition, as the size of the router increases, our solution also provides increased flexibility. Finally, we discuss the implementation issues involved in this new way of sharing the router processing power.