|M.Sc Student||Eshkoli Ayal|
|Subject||Design and Analysis of High Performance Inductors for|
Power Management Applications
|Department||Department of Electrical Engineering||Supervisors||Professor Emeritus Yael Nemirovsky|
|Dr. Shye Shapira|
|Full Thesis text|
High frequency power management circuits are increasingly being implemented in integrated silicon chips consistent with the decades-long practice of scaling down transistor size. Unlike Radio Frequency Integrated Circuits (RFIC), Power Management ICs (PMIC) still use off-chip inductors and capacitors. The values of these off-chip passive components are typically in the range of Micro-Henry and Micro-Farad[G1] . These values cannot be easily achieved by a standard CMOS process.
Power systems-in-package (PSiP) or Power System on Chip (PSoC), integrating all active and passive components into a single package or chip, provide a solution with a significant improvement in performance and reduction in board space, parts-count, and time-to-market. The inclusion of the passive components in one system with the PMIC makes the power supply design much more efficient as the tradeoffs between switching frequencies and inductance values can be worked out as a standard optimization by varying internal system parameters.
The present study is part of an ongoing research into a class of high performance inductors for broad band power management applications. Following the design, simulation, fabrication and measurement of new and innovative inductors, this study details and expands the theoretical background of a semi-empirical lumped-circuit model for cone shaped inductors for the first time. The model accurately describes the high performance of such inductors, which can be obtained commercially and are widely used by industry for broad bandwidth applications. The model provides a relatively simple design tool for such inductors up to the first resonance frequency and gives physical insight about the advantages of such inductors. This research also revolves around the integration of a planar inductor on a typical PMIC chip having several mm2 footprints, using a standard TOWERJAZZ 0.18[um] VLSI process. The design of an optimal PMIC with an integrated inductor requires mapping the parameter space of the joint PMIC and inductor system. The PMIC parameters, Input voltage, Output voltage, Switching frequency and currents through the inductor will determine the required inductance when the system optimization is carried out under the constraint of highest efficiency. Inductors with a high permeability core can immensely reduce the inductor size. However cores suffer from frequency dependent losses caused by skin depth, eddy currents, hysteresis, and displacement currents. A high resistivity core is then desirable to reduce eddy current losses. The challenge then is to find a cost effective means of integrating magnetic core inductors on-chip with the adequate performance parameters described above.