טכניון מכון טכנולוגי לישראל
הטכניון מכון טכנולוגי לישראל - בית הספר ללימודי מוסמכים  
M.Sc Thesis
M.Sc StudentSaher Odeh
SubjectNAND Flash Architectures Reducing Write Amplification
through Multi-Write Codes
DepartmentDepartment of Electrical Engineering
Supervisor Professor Cassuto Yuval
Full Thesis textFull thesis text - English Version


Abstract

Multi-write codes hold great promise to reduce write amplification in flash-based storage devices. In this work we propose two novel mapping architectures that show clear advantage over known schemes using multi-write codes, and over schemes not using such codes. We demonstrate the advantage of the proposed architectures by evaluating them with industry-accepted benchmark traces. The results show write amplification savings of double-digit percentages, for as low as 10% over-provisioning. In addition to showing the superiority of the new architectures on real-world workloads, the work includes a study of the write-amplification performance on synthetically-generated workloads with time locality. Moreover, the work is complemented by some analytical insights to assist the deployment of the architectures in real storage devices with varying device parameters. Finally, a full analysis framework is provided to calculate the write amplification for two novel and practically important scenarios: workloads with time locality, and devices with multi-write capabilities. The former captures a central feature of real-world workloads, while the latter addresses a promising feature likely to be added to next-generation solid-state storage devices.

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