טכניון מכון טכנולוגי לישראל
הטכניון מכון טכנולוגי לישראל - בית הספר ללימודי מוסמכים  
M.Sc Thesis
M.Sc StudentYuval Hai Nacson
SubjectPerformance and Energy Evaluation of Continuos Flow
MultiThreading Processors
DepartmentDepartment of Electrical Engineering
Supervisors Professor Emeritus Weiser Uri
Professor Etsion Yoav
Full Thesis textFull thesis text - English Version


Abstract

Memory elements are commonplace on the die of modern processors. Memory elements such as caches and data structures within the processors occupy more and more area of the die. However, as a memory element grows, so does its leakage power dissipation and the latency of the interconnect wires.

Over recent years, a number of memory technologies such as RRAM, STT-MRAM and PCM have emerged. Although they use different mechanisms, these technologies share some important properties. They are fast, highly dense and non-volatile. In addition, unlike current technologies such as DRAM and SRAM, they are located in the metal layers of the chip rather than in the silicon layer. These properties enable micro-architectures that were previously unavailable due to the limitations of current memory technologies.

Located in the metal layers, the emerging technologies are able to relieve the pressure on the area budget of the chip. Moreover, the proximity to the logic allows shorter wires between the memory elements and the logic. The non-volatility allows a large amount of data to be retained without the leakage power penalty that comes with current on-die memory technologies.

One of the applications enabled by the emerging memory technologies is the multistate register. The multistate register functions as a regular CMOS register except that it can also store multiple shadow values of the registers. Each of these values corresponds to one of the register states. The multistate register in turn enables the Continuous Flow Multi-Threading (CFMT) microarchitecture, an improvement on the Switch on Event (SoE) microarchitecture. In CFMT microarchitecture, the instructions filling the pipe are saved in the multistate registers upon thread switch, instead of being flushed out as in SoE.

In this thesis an evaluation of the performance and energy consumption of the CFMT is presented. We model the impact of the multistate registers in the pipeline and present analytical models for both performance and energy consumption. These models are then evaluated through an in-house performance simulator and McPAT power evaluation framework. The design space of the CFMT is then evaluated against SoE using the performance simulator and SPECCPU 2006 benchmark suite.