|M.Sc Student||Maria Malits|
|Subject||Study of Thermal Effects in CMOS-SOI Technology and|
|Department||Department of Electrical Engineering||Supervisor||Professor Emeritus Nemirovsky Yael|
|Full Thesis text|
CMOS-SOI technology is emerging as a promising solution to continue the CMOS scaling roadmap at the 22nm technology node and beyond, especially for low-power, high temperature and “system on chip” applications. Furthermore, CMOS-SOI technology is used in a wide range of applications where integrated CMOS-SOI-MEMS/NEMS technologies provide unique sensing systems for IR and THz imagers.
In spite of the inherent advantages, thermal effects in CMOS-SOI technology have been a major concern during design and operation of circuits in advanced technology nodes. The reason is that the low thermal conductivity of the buried oxide (BOX) in CMOS-SOI circuitry increases heating effects (self and coupled) and as a consequence have the potential to cause performance degradation, circuit instability, reduced maximum drain saturation current and increase in overall mismatch between transistors. In this research we developed a novel method to determine device temperature by using its threshold voltage as a "thermometer". For that purpose, we conducted a methodological characterization of the process temperature dependent parameters such as threshold voltage, mobility and non-ideality factor. Then, the resulting calibration of the process Vt(T) and dVt(T)/dT was used to determine the self-heating of larger devices.
Furthermore, we developed a thermal model which correlates between the drain current and the temperature rise in the channel, based on thermoelectric effects like Peltier and Thomson heating. Following this model, the device temperature can rise by approximately 100K when operation power of the order of 10-3 Watt is achieved. The methods proposed by this research offer an easy and low cost solution for thermal characterization of a process and its temperature dependent parameters, as it doesn't require any additional test structures or special testing equipment.