טכניון מכון טכנולוגי לישראל
הטכניון מכון טכנולוגי לישראל - בית הספר ללימודי מוסמכים  
M.Sc Thesis
M.Sc StudentKhasin Yevgeny
SubjectCharacterization of Single Photon Avalanche
Diode in CMOS Technology
DepartmentDepartment of Electrical Engineering
Supervisor Professor Emeritus Nemirovsky Yael
Full Thesis textFull thesis text - English Version


Abstract

Recent photonic applications require the acquisition of images at very low light-level conditions, at high speed and mainly at low cost. Only the emerging CMOS Single Photon Avalanche Diode (SPAD) imagers, which do not available commercially yet, may meet the requirements for exceptional time resolution and ultimate optical sensitivity, simultaneously, at low cost. Single photon avalanche diode, also known as the Geiger-mode avalanche photo diode, is a low intensity light signals detector which able to detect single photons, is integrated into a single pixel together with its readout circuitry, in CMOS process, to form an imager.

Avalanche photo diode is generally a p-n junction photodiode, which operates at reverse bias and under high electric field inside the depletion region (also termed as the active region and/or multiplication region), in order to achieve an internal gain. In Geiger mode Avalanche Photodiode, which is reverse biased above its junction’s breakdown voltage, the gain due to avalanche breakdown is so high that it could be treated as “infinite” for a single incoming photon. By correctly quenching the device in order to return it back from its saturation state, and output a single digital pulse, that will express that single incoming photon.

This research focuses on the design and characterization of a high performance single element of SPAD in state of the art standard deep sub-micrometer CMOS technology. This standard CMOS technology is the key factor of lowering the cost of the CMOS SPAD Imagers. Special effort was put on achieving the correct design for minimizing the detector’s noise, which in SPADs termed as the Dark Count Rate (DCR), and maximizing its quantum efficiency, termed Photon detection efficiency (PDE).

The tested designs were fabricated in standard 180nm CMOS technology. The electro-optical measurements and characterizations were accompanied with appropriate simulations that were made with computer software, as well as with theoretical analysis. In most cases, the simulations on the designs were made prior the fabrication, allowing focusing on designs of interest, which proved to achieve the best results, and further understanding of SPADs operation.