|M.Sc Student||Diamant Ron|
|Subject||Asynchronous Sub-threshold Ultra-low Power Processor|
|Department||Department of Electrical Engineering||Supervisors||Professor Ran Ginosar|
|Dr. Rakefet Kol|
|Full Thesis text|
Ultra low power VLSI circuits may enable applications such as medical implants and sensor networks. Aggressive supply voltage scaling is known to significantly improve power consumption and efficiency, but incurs both performance degradation and high delay variations. We illustrate that the most energy efficient operating point of a pipelined MIPS CPU lies in the sub-threshold region. We investigate the optimal selection of technology node, process variant and transistor type, and compare synchronous and asynchronous designs.
We identify the optimal performance/power ratio design point as the 28nm high-k metal-gate high-performance process with high VT transistors and a bundled-data asynchronous design style to efficiently accommodate delay variations. We illustrate a 7? power efficiency improvement potential for the CPU, coupled with a reduction in power consumption by more than one thousand, relative to a synchronous CPU operating at nominal voltage. The asynchronous sub-threshold MIPS CPU designed in this work is compared with other commercial and research CPUs, and is shown to achieve superior power efficiency.