|M.Sc Student||Mohammad Nassar|
|Department||Department of Electrical Engineering||Supervisor||Full Professor Ginosar Ran|
|Full Thesis text|
This work focuses on a simple micro-architecture of a many-core chip in order to analyze the trade-offs between three major design parameters: cache size, core count and core area. We study a simple micro-architecture for Chip Multi-Processor (CMP) architecture where it consists of an arbitrary number of identical processors and a shared cache. We derive a general objective function that links parallel processing performance to cache size (silicon area), single processor area and the total number of processors. Furthermore, we find the parameters that maximize the system performance defined by the objective function, under the total chip area constraint and the off-chip memory available bandwidth.