|M.Sc Student||Nahmanny Danniel|
|Subject||High-Speed, Currnet-Mode, Serial Link Communication|
|Department||Department of Electrical Engineering||Supervisor||Professor Ran Ginosar|
|Full Thesis text|
With the shrinking process of newly days technologies, on-chip global interconnect is becoming the bottle neck of vlsi design performance. Increased signal propagation delay between different on-chip modules, which are operating faster in scaled technologies, results in more on-chip parallel communication to enable these fast data transmission needs.
Although parallel communication is the easy solution for those fast transmission needs, it uses a lot of silicon area, high level metal area and it is power hungry. Serial communication can solve these issues but it can’t handle the fast transmission needs. Several techniques and architectures offer fast serial communication but they are usually limited to several gate delays, and they are quite complex to construct.
This research deals with fast on-chip serial communication that is capable of one gate delay differential signaling for long on-chip distances. The result is the fastest serial on-chip communication suggested today. A 28 Gbps transmission rate was proven in simulations, for a distance of 5mm in a 65nm lp technology.
A current mode based analog transmitter-receiver is presented. Current mode signaling is preferred over voltage mode since the low voltage swing over the channel enables faster transmission rate and is less sensitive to esd. On the transmitter side a differential current steering transmitter sends currents signals to the channel. A low input impedance regulated cascade receiver is implemented, translating the received currents to low voltage swing differential signals. A three level differential amplifier is connected to the receiver to amplify the signals to the digital serdes circuit at the receiver side. Post layout simulation of the analog transmitter-receiver shows, that 28Gbps transmission rate is possible.
To perform the link transmitting simulations an accurate line modeling technique is performed, which is based on electro-magnetic solution of the transmission line structure along with an improved RLC model structure. By that, more accurate and reliable simulation results were performed.
To prove this concept a test chip was planned and fabricated. The test chip consists of 14 links, with different transmission length (up to 4.5mm), using different metal layers, different layout implementation and different mode of operation (voltage/current).
Although an error in the chip’s digital controller synthesis disabled us from testing the chip, this novel architecture concept was proven in post layout simulations. Transmission rate of up to 28Gbps was achieved for the longest 4.5mm link.