|M.Sc Student||Visokolov Gil|
|Subject||CMOS Single Photon Avalanche Diode (SPAD) for Imaging|
|Department||Department of Electrical Engineering||Supervisor||Professor Emeritus Yael Nemirovsky|
|Full Thesis text|
Highly demanding photonic applications require the acquisition of images at very low light-level conditions and at high speed. Geiger mode CMOS imagers, where the sensor in each pixel is a Single Photon Avalanche Diode (SPAD), may meet the requirements for exceptional time resolution and ultimate optical sensitivity, simultaneously. Despite impressive progress, Geiger mode megapixel CMOS imagers are still not available commercially.
Recent research efforts focus on integration of low dark count rate (DCR) SPADs in state of the art deep sub-micrometer CMOS processes. This effort requires further scaling down of the CMOS SPAD technology and pixels, while achieving low dark count rate (noise), high photon detection efficiency (PDE) and high fill factor (FF). Traditional SPAD designs have failed to yield a scaled down, low DCR pixel while retaining high fill factor, high photon detection efficiency (digital quantum efficiency extension) and integration capabilities with in-pixel and on-chip circuitry.
This work presents the design considerations and simulations that create a novel SPAD fabricated in state of the art 0.18µm CMOS image sensor technology. The innovative design of a low DCR, high PDE SPAD is presented. Furthermore, analysis of the SPAD's transient nature leads to a new approach in determining of the optimal quenching resistor used in every SPAD pixel.