טכניון מכון טכנולוגי לישראל
הטכניון מכון טכנולוגי לישראל - בית הספר ללימודי מוסמכים  
M.Sc Thesis
M.Sc StudentShaham Oded
SubjectModeling Signal, Noise and Distortion in Photonic
Integrated Analog-Digital Converters
DepartmentDepartment of Electrical Engineering
Supervisor Professor Moshe Nazarathy
Full Thesis textFull thesis text - English Version


Abstract

Electronic Analog to digital Converters (ADC) are used today in almost every place digitization of analog signals is required. The capabilities of this kind of ADCs have progressed over the years, showing higher sampling frequency in some ADCs and better quantization resolution in others. While the demand for faster communication links is growing, the improvement trend in electronic ADCs has slowed in recent years due to several limitations. Two major limitations are the aperture jitter and the input bandwidth, which both limit the maximal sampled frequency.

Photonic Analog to Digital Converters (PADC) have been researched over the last decades, but no commercial ADC that uses photonics exists today. Improvements in the fields of high-speed electro-optic modulators and low jitter mode-locked-lasers open a way for PADCs to reach sampling frequencies and bandwidths unattainable by electronic ADCs.

In this work we explore PADC architectures which incorporate optical sampling and optical quantization. The voltage-under-test is encoded into phase-difference, and the phase-difference is quantized. Theoretical performance expressions are derived, taking into account random noises (shot and thermal noises), and are compared to simulation results. These results are upper bounds on the performance of such PADCs, as impairments weren't modeled in the simulations will cause degradation in the performance.

We introduce the phase comparator which is used to compare a phase-difference against a reference phase. We analyze the random noises in it, and can estimate the amount of optical power required to achieve any desired output resolution.

FLASH PADC architecture is presented and also novel Successive Approximations Register (SAR) architecture. For both architectures we address the error sources and compare the theoretical performance to the simulation results. We explore the error propagation in the SAR architecture, and analyze the impact of jitter on its expected performance.

Pipelined-SAR architecture is also presented. It is based on the SAR PADC scheme, and should be more power efficient. This architecture has new noise sources, and the design must take into account the cyclic nature of phases which can result in large output errors. In the proposed architecture each element in the pipeline can correct small errors occurred in the previous element, thus the architecture has the potential to exhibit high performance.