|M.Sc Thesis||Department of Electrical Engineering|
|Supervisor:||Assoc. Prof. Ginosar Ran|
|Full Thesis text|
HyperCore is a simplistic architecture enabling 100-1000 cores to achieve higher performance than multicore. It comprises on-chip shared memory (organized in many banks), simple cache-less RISC cores and a simple on-chip hardware scheduler, using a single slow clock. This simplistic approach eliminates coherency issues, key to integrating many cores. This study concentrates on improving network to eliminate the slow-clock limitation. We study a modified HyperCoreX architecture with a non-equidistant network to memories, allowing shorter access times to nearer memory banks from cores and memory banks point of view. Six benchmark programs were employed, representing a wide variety of inherent parallelism, address distributions, access rates and data sharing. It was shown that the non-equidistant memory in HyperCoreX, together with the resulting increase of frequency, can speed up program execution by 4-9 times relative to the equi-distant single cycle architecture, and thanks to new concept called path-latency diversity, can reduce memory wait time by up to 61%.