טכניון מכון טכנולוגי לישראל
הטכניון מכון טכנולוגי לישראל - בית הספר ללימודי מוסמכים  
M.Sc Thesis
M.Sc StudentBerman Amit
SubjectPower Reduction Techniques for Networks-on-Chip
DepartmentDepartment of Electrical Engineering
Supervisor Professor Idit Keidar
Full Thesis textFull thesis text - English Version


Abstract

Modern Network-on-Chip (NoC) links consume a significant fraction of the total NoC power, e.g., one study has shown that they consume up to 60% of total power and that this fraction is apparently growing. We present two algorithms for power reduction in NoC links.

We first present Parity Routing (PaR), a novel method to add redundant parity information to packets, while minimizing the number of redundant bits transmitted. PaR exploits NoC path diversity in order to avoid transmitting some of the redundant parity bits. Our analysis shows that, for example, on a 4x4 NoC with a demand of one parity bit, PaR reduces the redundant information transmitted by 75%, and the savings increase asymptotically to 100% with the size of the NoC. In addition, we show that PaR can yield power savings due to the reduced number of bit transmissions. Furthermore, PaR utilizes low complexity, small-area circuits.

Second, we present Selective Packet Interleaving (SPI), a flit transmission scheme that reduces power consumption in NoC links. SPI decreases the number of bit transitions in the links by exploiting the multiplicity of virtual channels in a NoC router. SPI multiplexes flits to the router's output link so as to minimize the number of bit transitions from the previously transmitted flit. Analysis and simulations demonstrate a reduction of up to 55% in the number of bit transitions and up to 40% savings in power consumed on the link. SPI benefits grow with the number of virtual channels. SPI works better for links with a small number of bits in parallel. While SPI compares favorably against bus inversion, combining both schemes helps to further reduce bit transitions.