|M.Sc Student||Inna Vaisband|
|Subject||Power Efficient Tree-Based Crosslinks for Skew Reduction|
|Department||Department of Electrical Engineering||Supervisors||Full Professor Ginosar Ran|
|Professor Emeritus Kolodny Avinoam|
|Full Thesis text|
Clock distribution networks are an important VLSI design component that distribute the clock signal from a common point to sequential logic within a circuit and in this way enable its synchronization. Clock propagation delays within a distribution network vary from path to path due to load imbalances, different wire lengths, and under process, voltage and temperature (PVT) variations, exhibiting skew within clock arrivals at sequential elements. Traditional clock tree based techniques, such as buffer insertion and sizing, as well as wire sizing and segmentation, were successfully used for decades to reduce skew. However, the severity of clock skew problem is measured relatively to the clock period; thus, reducing skew under continuous speedup of design frequencies become a great challenge during the last years. High switching factor and significant capacitance of clock distribution networks dictate the necessity of power efficient solution for skew reduction in synchronous designs.
Lately, non-tree clock networks became very popular for skew mitigation in synchronous digital circuits. Non-tree topologies vary from a single crosslink that shortens two nodes within a clock tree to a full mesh that connects a significant group of adjacent nodes. Mesh topologies appear to be very convenient for skew reduction. However, the significant increase of total wire length in full mesh-based clock network implies very high additional power cost. Alternatively, existing link based methods only address skew caused by variations and do not consider power consumption.
The power dissipated by the inserted crosslinks within a buffered clock tree is investigated in this paper, and is shown to be a strong function of the resistance and capacitance of the crosslink. A crosslink may be power efficient despite the presence of short-circuit currents caused by multiple drivers in a non-tree clock network. The power characteristics of crosslink size and placement are also discussed, showing that the crosslink is best placed as close as possible to the target leaves of the tree. Crosslink insertion as both an alternative and complement to buffer sizing for low power skew reduction is also considered.