The aim of this
research is to study and understand how the composition of the high-k
dielectric materials affects the electrical and material properties as well as
the thermal stability of metal/high-k/Si stacks. This research focuses on three
systems of dielectric films. The first system is Al2O3,
which is a promising candidate in memory applications, where the low
leakage current is the major requirement for the charge storage. The influence
of the substrate on the interface properties of the dielectric/Si stack, effect
of oxide structure on the band gap and dielectric constant were studied. The second
system is HfxSi1-xO2N for x=0, 0.3, 0.5, 0.7
and 1, which is suitable for gate dielectric. It was found that the addition of
Si and N to HfO2 increases the crystallization temperature, the band
gap and valence band offsets relative to Si, however, it decreases the
dielectric constant of the Hf-based films. Therefore, an optimal composition
needs to be found in order to use these oxides as gate dielectrics. During thermal
treatment at 800˚C, the oxides with higher Hf content separate to
amorphous SiO2 and crystalline HfO2 phases with a
monoclinic structure. In addition, Pt diffuses though the Hf silicate films and
SiO2 layers to the Si substrate where Pt silicide is formed in the
samples. The third system is (TbxSc1-x)2O3.
The rare earth oxides are also candidates for gate dielectric replacement. Isomorphic
miscibility of the rare-earth oxides opens possibility to mix these oxides. An
interfacial layer formation was observed at the oxide/Si interface for all
compositions. The study shows that the mixing influences the band gap and
dielectric constant. It also helps to reduce water absorption, but does not
influence the valence band offset. It is possible to tune the properties of
functional oxides for future nanoscale devices. The addition of a third element
into binary oxides helps to achieve the desired properties of the alternative
high-k materials, such as high dielectric constant, high band gap, suitable
band offsets relative to Si, amorphous structure, low leakage current, low
density of the electrical defects and compatibility with current CMOS
processing.
