טכניון מכון טכנולוגי לישראל
הטכניון מכון טכנולוגי לישראל - בית הספר ללימודי מוסמכים  
M.Sc Thesis
M.Sc StudentNisan Lati
SubjectMinimizing Idle Times in Cluster Tools in the Semiconductor
Industry
DepartmentDepartment of Industrial Engineering and Management
Supervisors Professor Herer Yale
Professor Gilad Issachar
Full Thesis text - in Hebrew Full thesis text - Hebrew Version


Abstract

This thesis is dedicated to the problem of sequencing handler’s moves in cluster tools in the semiconductor industry.  Suboptimal sequence of the handler’s moves usually leads to long idle times in the cluster tool’s chambers and hence longer makespan. Therefore an effective algorithm that minimizes idle times in the cluster tool’s chambers is required.  An algorithm called MinBIT (Minimizing Bottleneck Idle Time) is presented as a new method for sequencing the handler’s moves. The MinBIT algorithm gives priority to the bottleneck stage, and thus leads to a reduction in unnecessary idle times and hence a shorter makespan.

We compared the MinBIT algorithm with other algorithms.  Our algorithm achieved best performance in 98% of the cases.  In the other 2% of the cases it achieved second or third best performance. The computational results show that the MinBIT algorithm can improve the performance of a cluster tool by up to 10%.  Comparison between the MinBIT solutions and the optimal solutions, found by using Branch & Bound, show that the deviation between them ranged between 0% and 0.22%, which indicates that MinBIT gives an optimal or near optimal results.