This
thesis presents two related topics: a novel design methodology for improving
the noise figure of a Ka band LNA (24GHz), and a comprehensive study of slow
wave transmission lines that were incorporated in the circuit. The LNA achieved
a record low 2.8 dB noise figure, 1 dB lower than state of the art LNA
fabricated using the same 0.18 µm CMOS technology. The obtained noise figure is
comparable to the performance of LNAs fabricated using more advanced silicon
technologies such as 90 nm CMOS and SiGe heterojunction bipolar transistors.
The salient result presented in the section on slow wave transmission lines in
this thesis is a new compact analytic model that accurately describes the
properties of slow wave transmission lines. The model also provides straight
forward physical insight on the principle of operation of slow wave
transmission lines. The essence of the design methodology presented in this
thesis is that the transistor current density is determined at an early stage
of the design, and transistor gate width only in the last stage. This
methodology is based upon the experimental observation that the noise and gain
characteristics of the device are primarily determined by the current density.
As in most previous studies, we have chosen the inductive source degeneration
common source topology, which provides low noise figure and high gain with
simple matching networks. The optimal value of the source denegation inductance
was determined prior to determining the transistor gate width, for several reasonable
gate width values. The insertion loss of the input matching network for
different transistor width values was studied, and as mentioned above, only in
the last stage the transistor width was determined. The loss of the passive
elements in the LNA was reduced using slow wave transmission lines instead of
conventional transmission lines or spiral inductors. Slow wave transmission
lines exhibit a higher effective dielectric constant than standard transmission
lines. Thus, matching elements incorporating slow wave transmission lines are
shorter than the equivalent conventional elements, and their loss is
significantly lower. Chip size is also reduced by using slow wave transmission
lines instead of conventional transmission lines.
