|M.Sc Student||Aizik Yoni|
|Subject||Design Considerations for Low Power CMOS Digital Circuits|
|Department||Department of Electrical Engineering||Supervisor||Professor Emeritus Avinoam Kolodny|
|Full Thesis text|
Modern VLSI design requires a tradeoff between circuit speed and power dissipation. Timing optimization methods typically lead to excessive power consumption. In this work, we explore the energy/performance design space in CMOS circuits, to find gate sizes which produce the lowest possible power for any specified circuit delay. The tradeoff between energy and performance is achieved by relaxing the timing of the circuit through downsizing of the cells while preserving the circuit topology, thus reducing the active energy dissipation. Our analysis method is based on the commonly used logical effort methodology, extended to model power as well as delay. We introduce the energy/delay gain (EDG) notation, which measures the energy reduction rate that is achievable for each delay increase that is acceptable by the designer, and the local EDG (LEDG) property, as a metric for choosing an operating point on the EDG curve, while avoiding excessively low marginal costs. The power reduction process is applied to several typical circuits in 65nm technology, and power reduction of up to 25% for delay increase of 5% (EDG=5) are demonstrated. Most of the energy savings occur at the final stages of the circuits, while the largest relative downsizing occurs in middle stages. Typical tapering factors for power efficient circuits are larger than for speed-optimal circuits. Signal activity factors affect the optimal gate sizes in the combined optimization of speed and power. The proposed analytical method is shown to be accurate when compared to simulation based numerical optimization, and orders of magnitude faster.