|M.Sc Thesis||Department of Electrical Engineering|
|Supervisors:||Prof. Cidon Israel|
|Prof. Idit Keidar|
|Full Thesis text|
Network-on-Chip is an interconnect paradigm gaining increasing popularity and research interest in the academic and silicon-industry world. The basic idea behind NoC is to connect the functional modules of the chip using a network, which is built within the chip instead of traditional interconnect techniques like buses or point-to-point wires.
FPGAs are VLSI devices that allow configuring their logical functionality, thus can be used for many designs. FPGAs are popular in small and medium volume systems, like military or medical systems. They combine re-configurability and performance that traditional programmable devices like processors cannot cope with. In the last decade, FPGA have grown from several tenths of programmable elements (usually consist of a look-up-table and D flip-flop each), to many thousands of such elements in addition to special purpose modules like processors, multipliers and complex interfaces. The elements are interconnected using programmable routing matrix. As FPGAs’ density continues to grow, traditional routing matrices do not provide the required performance with low cost. In this thesis, we propose a NoC-based architecture for programmable chips.
A key challenge for FPGA design is supporting numerous highly variable design instances with good performance and low cost. Our architecture minimizes the cost of supporting a wide range of design instances with given throughput requirements by balancing the amount of efficient hard-coded NoC infrastructure and the allocation of “soft” networking resources at configuration time. Although traffic patterns are design-specific, the physical link infrastructure is a performance bottleneck, and hence should be hard-coded. It is therefore important to employ routing schemes that allow for high flexibility to efficiently accommodate different traffic patterns during configuration. We examine the required capacity allocation for supporting a collection of typical traffic patterns on such chips under a number of routing schemes. We propose a new routing scheme, Weighted Ordered Toggle (WOT), and show that it allows high design flexibility with low infrastructure cost. Moreover, WOT utilizes simple, small-area, on-chip routers, and has low memory demands.