טכניון מכון טכנולוגי לישראל
הטכניון מכון טכנולוגי לישראל - בית הספר ללימודי מוסמכים  
M.Sc Thesis
M.Sc StudentKayam Michael
SubjectSynchronizers for Low Voltage and Low temerature Operation
DepartmentDepartment of Electrical Engineering
Supervisor Professor Ran Ginosar
Full Thesis textFull thesis text - English Version


Abstract

Modern System-On-Chip (SoC) designs usually contain multiple asynchronous clocks, passing signals and data across those clock domains. These signals are often subject to the effects of metastability. Therefore, there is a necessity to synchronize data transfers between clock domains and, as a result, synchronizers are an essential part of any SoC design.

A detailed analysis of existing synchronizer circuits are presented in this study. Two novel synchronizers that bring a significant improvement to synchronizer performance under conditions of low supply voltage and temperature are proposed.

A few patented synchronizers are analyzed in this study. Some of the synchronizers are provided with “fault scenarios”, i.e. conditions that might cause the synchronizer to fail.

Some of the reviewed synchronizers are simulated. The simulations are performed using SpectreS simulator and BPTM 70nm process transistors.

Both the threshold voltage of a transistor and its carrier mobility decrease with temperature increase. Lower threshold voltage increases drain current, but lower mobility decreases it. The actual drain current is determined by which of these two competing processes dominate at a given bias voltage and temperature. The delay of a logic gate, which operates at low supply voltage, increases as the ambient temperature decreases, since it inversely depends on the bias current. The resolution time constant τ significantly increases at low temperature and low supply voltage. Hence metastability becomes a more severe problem in such conditions.

The Shaker latch employs a pulse that is applied to one of the latch nodes (“shakes” it), thus enabling faster resolution. The Dual Shaker latch is an improved version of the Shaker latch, which supplies an additional pulse to other node of the latch, some time after the first pulse. If the first pulse pushes the latch into metastable state, the second one helps it resolve. The Symmetric Boost latch is a version of the Dual Shaker. It applies two simultaneous pulses to both nodes of the latch, thus dynamically increasing the transconductance of the latch transistors, and decreasing the resolution time constant τ of the latch. The simulation results of the Dual Shaker and the Symmetric Boost latches that are presented here show that these circuits are capable of operating in conditions of very low temperature and low supply voltage.