|Ph.D Thesis||Department of Materials Science and Engineering|
|Supervisor:||Prof. Eizenberg Moshe|
|Full Thesis text|
The drive towards increased speed and functionality of microelectronic devices has led to their miniaturization. The main speed limitation of integrated circuits today results from time delay of electrical signals passing through the interconnects - those conducting wires that connect between the different components in the circuit. As the dimensions of copper interconnects approach the mean free path of the electrons (~40 nm at room temperature) a substantial rise in their resistivity occurs, which slows the circuit. This resistivity increase is in the focus of this study.
The results show that the two key factors influencing the resistivity increase are surfaces and grain boundaries. These effects are first studied on thin films and then on real interconnect wires.
An analytical model is developed for the temperature dependence of resistivity in nanometric dimensions. It is shown that temperature and dimensions are correlated, and thus resistivity measurements that are performed at low temperatures correspond to smaller dimensions at room temperature.
As the grain size decreases, the volume of the grain boundaries increases, and their influence on the resistivity is more pronounced. It is shown that the average grain size is the important factor, together with the reflection properties of the grain boundaries.
The effect of surface roughness is studied using a new experimental technique, in which copper films are measured during etching. The results show that as the roughness increases and is larger than the de-Broglie wavelength of the electrons, a substantial increase in resistivity occurs.
The role of interfaces is studied using a special tool that enables in-situ resistivity measurements inside a sputtering deposition chamber. The resistivity of copper films is monitored when a new interface is created on top of them, giving a unique observation. It is shown that choosing the proper interface can significantly reduce the harmful resistivity increase.
Finally, the resistivity of nanometric copper wires in a real interconnect geometry is investigated, using the above-mentioned insights. A detailed model is developed to explain the resistivity of wires and to extract meaningful parameters. The importance of interfaces to the resistivity of wires is demonstrated, in addition to the effect of grain boundaries. Apart from the scientific value, the results supply significant information for the development of low resistivity interconnects, that are needed for faster integrated circuits.