טכניון מכון טכנולוגי לישראל
הטכניון מכון טכנולוגי לישראל - בית הספר ללימודי מוסמכים  
M.Sc Thesis
M.Sc StudentKapchits Anastasia
SubjectModeling and Design of Network on Chip Interconnects
DepartmentDepartment of Electrical Engineering
Supervisors Professor Emeritus Avinoam Kolodny
Dr. David Goren


Abstract

On-chip packet-switched network can potentially become the preferred interconnection approach for future Systems-on-Chip (SoC).  These on-chip networks provide efficient sharing of global wires, which can be structured so that their electrical properties are optimized and well-controlled. Physical design and modeling aspects of Network on Chip (NoC) links are described. A typical link configuration consists of a number of parallel wires forming a point-to-point connection, without tree structures as in general interconnect. The geometry parameters of the link such as spacing and width of wires determine the wire electrical parameters namely the capacitance, resistance and inductance per unit length. These geometry parameters of the link can be designed to obtain optimal performance parameters. The data rate is chosen to be the optimization metric for NoC link. At the first step of the work, link analysis using RC wire model is performed. The analysis is done first for ideal drivers, then real drivers are included in the analysis and results are compared. For RC wire models, the optimal link dimensions can be expressed by normalized parameters, i.e. scaling the wire cross sectional dimensions preserves the optimum. A simplified analytical approach for calculating optimal link parameters is shown.

Inductive effects are investigated, and the results of RC and RLC analysis are compared. It is shown that maximal data rate is achieved near the boundary between RC and RLC model validity domains. Based on this result, a simple design criterion is presented for obtaining maximal data rate in NoC links. The criterion is applicable to various on-chip transmission line structures, including crossing lines at adjacent metal levels.

Microstrip transmission lines are used as an implementation for NoC link wires. Bottom shielding isolates silicon substrate effects, provides well defined current return path and enables simple inductance calculations.  On-chip transmission line models, used in analog circuits, include frequency dependent phenomena such as skin effect and silicon substrate related effects. These models are not practical in digital circuits due to large number of wires and long calculation time. A simple model without frequency dependent phenomena is developed and verified by circuit simulations. For digital circuits, a design approach to reduce the frequency dependent phenomena in transmission lines is presented, enabling the use of this simple model.