|M.Sc Student||Fiksman Evgeny|
|Subject||Dynamic Reconfiguration Architectures for Multi-Context|
|Department||Department of Electrical Engineering||Supervisor||Professor Yitzhak Birk|
|Full Thesis text|
Field-programmable gate arrays (FPGAs) are used whenever quantities and/or development time do not justify ASICs, as well as for prototypes. They are also an effective means for (hardware) flexible high-performance computing. As part of the general “System on Chip” trend, there is a clear trend to combine ASIC efficiency with FPGA versatility. One example is the Xilinx® Virtex®IV devices that integrate custom logic, fixed DSP processors, network cores and even general purpose CPUs. Others are the AMD® Opteron™ and Intel® Xeon™ dual-processor motherboards, wherein one of two processor slots can be populated with an FPGA. Finally, future multi-core processors are expected to include a reconfigurable part. Software vendors are also addressing this trend by providing comprehensive tools for mixed SW/HW development, e.g., the ASC library by Maxeller.
The aforementioned “mixed” architectures feature great flexibility, but many applications do not use the “FPGA” part efficiently because different functions are required at different times. (Negative implications include cost and static power.) Indeed, FPGA vendors have begun to permit part of an FPGA to be reconfigured while other parts are operating, but the reconfiguration is slow and inapplicable for frequent changes.
Our work, motivated by the idea of DLLs in software, is aimed at exploring the possibility of “hardware DLLs” by finding ways for fast dynamic incremental reconfiguration of FPGAs. We propose two new multi-context FPGA architectures based on two different storage architectures: local and centralized. We used well known area and power models in evaluating various approaches and in order to match architectures to target applications. This work is a necessary step, providing the foundation and “rules of the game” for the subsequent development of reconfiguration schedulers and execution environments.