|M.Sc Thesis||Department of Electrical Engineering|
|Supervisor:||Assoc. Prof. Ginosar Ran|
|Full Thesis text|
In a metastable state, the output voltage of a flip-flop lies in the middle between the two legal logic states. The flip-flop may enter that state if the data is changed within the setup-hold time window around the sampling clock edge.
That time window can be divided into three main regions: Synchronous, deterministic and deep metastability. Some events are “almost” synchronous, i.e., they propagate to the output similarly to normal synchronous events. Events in the deterministic region propagate to the output slower than the normal propagation delay of the flip-flop. Events in the deep metastability window, which is very narrow in size, may cause the flip-flop to become metastable, so that its output is “stuck” in between the legal states. The main difference between deterministic and metastable events is that in the former case the output converges to the value of the input after some delay, while in the latter case the output eventually converges in random to either ‘0’ or to ‘1’ with equal probability.
The metastability as a process can be described by a model dependent upon the metastability time constant. In this work, a novel method for measurement of this time constant was investigated. The results of the measurement were compared to the results obtained by previously existing methods and were found to be similar, with some new findings that were never published before.