|M.Sc Student||Veinblat Alexander|
|Subject||Analog Convolutional Decoder|
|Department||Department of Electrical Engineering||Supervisor||Professor Emeritus Israel Bar-David|
This thesis is about using the analog circuits for decoding convolutional codes (CC). One of the advantages of CC is the ability to encode very long information sequences and the other is good utilization of the channel capacity. Also it is possible to begin the decoding of a long encoded block upon receiving only a portion of it. Because of their good properties, CC are widely used for error correction in communication and data storage systems. The demands of the times are increasing data transmission rates. Modern fiber optic channels are capable of transmitting data at a rate of several dozen gigabits per second. Most present-day (2002) decoders are digital and do not meet the requirements to handle so high a data rate. Introduction of turbo codes are built around CC and are capable of operating near the channel capacity, which only increases requirements to the digital decoders.
To overcome the limitations of digital decoders, several analog decoding schemes were proposed since 1997. The approach was to find a correspondence between equations, describing non-linear properties of transistors, and equations, used in decoding algorithms. For example, it was noted, that Gilbert current multiplier, known for more than 30 years, exactly relates to the probability equation of a XOR (exclusive-OR) element that is used as a basic element for CC encoders.
Analog decoders have some merits over digital decoders. The most important of them is the ability to perform decoding during the transient process in analog networks. One can consider an analog decoder as an analog network. This network has, after applying its inputs, a transient process leading to a final state. Analog decoders are designed in a way that this final state corresponds to the decoded information sequence.
The demerit of analog decoders is the limitation of the length of the CC coded block. Most of the analog decoders are designed in a way that a whole code block must fit in their analog networks. That is, the length of the CC block determines the size of analog networks and in the case of long blocks they are not feasible.
This work presents a new analog decoding technique to overcome this limitation. The technique makes use of the known property of CC that only a portion of a code block may be sufficient for beginning the decoding process. So it is possible to build an analog network for performing the decoding of CC that contains only a portion of the code block at the same time.
The technique uses a closed analog calculation chain and a special order for applying inputs to it. The inputs are applied in a way that the chain operates as a sort of pipeline. Because of the pipelined type of functioning it is possible to achieve an overall processing speed higher than that of a single unit in the analog calculation chain.
The performed simulations confirmed our assumptions about good properties of the proposed technique, called “Ring Decoding” according to the shape of the analog calculation chain. This work may form a basis for new analog decoding schemes using the proposed “analog pipeline” idea.