|M.Sc Student||George Shchupak|
|Subject||High Speed, Low Power Medium Size Cache Design|
|Department||Department of Electrical Engineering||Supervisor||Professor Emeritus Kolodny Avinoam|
Growing demand for faster
microprocessors pushes operation frequencies into 2GHz range, thus increasing
power consumption of the chips. On the other hand, battery lifetime and overall
system cost impose limitations on power dissipation. Therefore circuit design
techniques should consider both speed and power consumption.
Existing circuit design methods involve numerous “trial & error” iterations in order to achieve timing and power consumption goals. The method of Logical Effort, provides an algorithm for “correct by design” path optimization. The method simplifies the process of evaluation of various possible implementations of a given circuit structure. In the field of power estimation there exist several approaches. Most of them require heavy simulations over numerous test patterns in order to calculate the average power consumption. The technique described in this work is a power estimation technique based on switching activity of signals. It allows fast estimation of power consumption of relatively large functional blocks. The technique doesn’t require pattern based simulations, thus reduces the time needed for power estimation.
This work reports on the design of a medium size cache aimed to achieve fast operation at low power within an industrial CPU chip. The method of Logical Effort is used to compare different design implementation options of various parts of the cache. Estimation of power consumption is made by applying switching activity based techniques. Timing and power optimization results are shown.