|M.Sc Student||Barsky Roman|
|Subject||Electromigration-dependent Parametric Yield Estimation|
|Department||Department of Computer Science||Supervisor||Dr. Israel Wagner|
In this work we introduce a model for VLSI reliability in terms of a special kind of yield problem. Usually, the term VLSI yield can be defined as the ratio of the number of chips that are usable after completion of production to number at start of production that have the potential to be usable. The term usable is usually interpreted as complying with all logical specifications, and such yield is called catastrophic yield.
Wagner and Koren in the paper "The Effect of Spot Defects on the Parametric Yield of Long Interconnection Lines" discuss the parametric yield, in which the question is: "How many chips will have an acceptable performance?". The term acceptable performance may have different interpretations, e.g. frequency, power consumption, Mean Time To Failure (MTTF), etc. In their paper they develop an approach to estimate the frequency dependant yield of long interconnect lines.
In this work we focus on electromigration-dependent parametric yield (EPY), where one is concerned about the number of chips that will survive electromigration for a given period of time. EPY is a function of layout geometry, the desired MTTF, and current flow data, along with working temperature, metal properties and some other process data. The proposed analysis attempts to evaluate the projected ratio of chips complying MTTF target to all the chips that found to be "usable" as defined above.
Analytical solution is given for simple layout and simulations for a more complicated case.