|M.Sc Student||Moreinis Michael|
|Subject||Repeater Insertion in Deep Sub-Micron VLSI Circuits|
|Department||Department of Electrical Engineering||Supervisor||Professor Emeritus Avinoam Kolodny|
As VLSI Technology scaling advances into Deep Sub-Micron dimensions, on-chip interconnect becomes a dominant factor in circuit design. One of the most powerful techniques for interconnect timing optimization is repeater insertion, introduced into VLSI in the early 90’s. Methods and algorithms of buffer insertion for specific purposes have been published, but there is still no comprehensive approach for incorporating repeater insertion into the circuit design process.This research presents several improvements to Repeater Insertion as a primary technique for timing optimization. In addition, Repeater Insertion is charactarized for other design objectives. A timing-driven design flow integrating considerations such as accurate modeling, noise, power and area, is described.
LGR (Logic Gates as Repeaters) - a methodology for delay optimization of CMOS logic circuits with RC interconnects was described. The traditional interconnect segmentation by insertion of repeaters is generalized to segmentation by distributing logic gates over interconnect lines, reducing the number of additional, logically useless inverters. The application methodology of LGR and related optimization methods were presented. Combination of Repeater Insertion with LGR (RI&LGR) is presented, providing methodology for delay optimization of CMOS logic circuits with RC interconnects, where the wire is segmented by distributing logic gates over interconnect lines and adding a reduced number of repeaters.
research showed that Repeater Insertion,