|M.Sc Student||Obridko Ilya|
|Subject||Minimal Energy Asynchronous Adder Architectures|
|Department||Department of Electrical Engineering||Supervisor||Professor Ran Ginosar|
As more portable and implantable electronic digital devices are introduced, the energy required for their operation is becoming a significant issue. This work focuses on reducing energy dissipation and extending battery life. Most previous published research deals with power optimization, while energy is treated less frequently. Power optimization assumes given performance requirements. Energy optimizations can include lowering computation speed. Many portable “slow” applications exist, such as hearing aids and pace-makers. Our research is directed at this field of applications. We employ speed independent adders, enabling circuit operation over a wide range of the supply voltages, which is typical in battery operating devices. We consider four published low power adders: The Martin’s, Nielsen’s, Chong’s, and PTL adders. We develop three novel low energy adders, creating large combinational blocks, minimizing the use of pipeline registers, and avoiding redundant transitions. We take advantage of the Carry signal, minimizing the amount of charge deposited on the diffusions. We use dual-rail logic on critical paths to get completion detection indication, but save energy dissipation using single-rail elsewhere. The proposed adders are analyzed by circuit simulations. Dynamic energy, short circuit energy and leakage energy contribute to the total energy consumption. Leakage energy is a small portion of the total energy dissipation in 0.18u and in older technologies. We estimated the significance of the SC energy using a chain of inverters and found that in most cases it cannot be ignored when estimating energy dissipation. Our Minimum Energy Dual-Bit Dynamic adder achieves 10% to 40% in energy savings and above 60% of speed-up compared to the other adders.