|M.Sc Thesis||Department of Electrical Engineering|
|Supervisor:||Assoc. Prof. Ginosar Ran|
Synchronization in digital circuits is a challenging topic that has been investigated intensively. Most approaches to the subject were limited to paper-designs and analytical studies. Actual laboratory measurements and in-depth analysis of synchronizers have been performed in very few cases.
The increasing use of GALS (Globally Asynchronous Locally Synchronous) design methodology has created a strong need for adaptive multi-synchronous synchronizers for high bandwidth data transfer. Existing solutions found in the literature are usually ‘full -custom’ oriented, very few detailed solutions are found for ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array) designs methodologies.
An experimental system and a method for measuring synchronizers and metastable flip-flops are described. The above system was first used for demonstrating synchronous sampling of a flip-flop. Clocking cross-talk between asynchronous clocks was demonstrated. The data-analysis method for computing a flip-flop’s time resolution constants is also described. Using this method, metastable behavior of an Integrated Flip-Flop and an FPGA Flip-Flop were analyzed, and the findings were shown to fit previously published results.
A regular (two-flip-flop) synchronizer and six multi-synchronous synchronizers were implemented on a programmable logic device and were measured. The synchronizers were designed for FPGA, and could be easily converted to ASIC or full custom design. The internal design of the synchronizers is described in this work in details.
The different synchronizers are compared in the hardware-occupancy, latency, throughput and adaptation-mode measures. The regular two-flip-flop synchronizer is useful for communication between asynchronous clock domains. The other synchronizers can provide higher bandwidth communication between clock domains in which the clock frequencies are close (or identical), yet there exists a slowly drifting phase difference between the clocks. A Clock-Delay synchronizer is shown to have the smallest hardware-occupancy among the synchronizers that support maximum throughput.