טכניון מכון טכנולוגי לישראל
הטכניון מכון טכנולוגי לישראל - בית הספר ללימודי מוסמכים  
M.Sc Thesis
M.Sc StudentAssad Khamaisee
SubjectCombining Trace Cache with Value Prediction in
Microprocessors
DepartmentDepartment of Electrical Engineering
Supervisors Full Professor Mendelson Avi
Professor Emeritus Kolodny Avinoam


Abstract

Trace cache and value prediction aim to improve the performance of advanced, wide processors. Trace cache increases the effective fetch bandwidth, while value-prediction mechanism breaks data dependencies by predicting the output of an instruction; thus, dependent instructions can be executed speculatively in parallel. Combining these two techniques, theoretically can achieve maximum utilization of the processor resources. But in practice, if the value prediction is too aggressive and produces too many speculative operations, a limited resources system may suffer from delaying “useful instructions” (which create the program’s critical path) by other usefulness operations.

This work proposes a simple, low-cost hardware method, which dynamically detects the program-critical instructions using the trace cache. The frequently fetched traces, which will be called “hot traces”, are identified. The hot instructions belonging to hot traces are repeatedly executed; therefore, we consider them as the program’s ‘critical’ instructions and limit the value prediction to those instructions belonging to these hot traces.

This work, explores the behavior of the data prediction mechanism attributes (hit rate, miss rate) across different predictor types and benchmarks. While the overall performance enhancement measurements are left for future work. Experimental simulation results show that this associative technique yields 60% prediction hit rate improvement and reduces the data prediction tables access rate approximately by 55%, compared with the data prediction base model.