טכניון מכון טכנולוגי לישראל
הטכניון מכון טכנולוגי לישראל - בית הספר ללימודי מוסמכים  
M.Sc Thesis
M.Sc StudentNir Magen
SubjectPower Issues of On-Chip Interconnect in VLSI
DepartmentDepartment of Electrical Engineering
Supervisors Professor Emeritus Kolodny Avinoam
Professor Emeritus Weiser Uri


Abstract

This research analyzes the interconnect power in microprocessors. The power dissipation due to a microprocessor’s interconnect has not been quantified, prior to this work. This work’s goals are to determine the importance of on-chip interconnect power, to characterize the power consuming interconnections, and to suggest and evaluate potential methods for interconnect power reduction.
The research is based on a case study evaluation. A state-of-the-art processor designed for low-power was analyzed for dynamic power consumption and its interconnection characteristics. Future generations processors’ interconnect power was predicted using existing interconnect length prediction models, calibrated using the extracted data. The interconnect characteristics were analyzed in an attempt to identify interconnect power saving opportunities. The interconnect power saving methods were evaluated by theoretical analysis and experiments in physical design aimed at reducing the interconnect power for blocks of the analyzed processor.

Results show that the on-chip interconnections consume the majority of the on-chip dynamic power, above 50%. The clock delivery network is the major interconnect power-consuming network, consuming about 40% of the interconnect power. The global communication lines, defined to be interconnections between architectural units, consume more interconnect power than the rest of the nets, although there are orders of magnitude less global lines than local lines. The future trends of the interconnect power were projected using several interconnection prediction models. All the models predict an increase of the relative amount of interconnect power as technology scaling advances. Due to the importance of interconnect power, this work suggests interconnect-power-aware design flow modifications at all the design levels: Optimizing the interconnect’s dimensions at the fabrication level can save up to 20% of the dynamic power, an interconnect-power-aware physical design is suggested, that can save up to 50% of the interconnect power. An example for architectural interconnect power evaluation is presented. In a design experiment, several interconnect-power-aware features were added to an existing router, creating a novel power-aware router. The main techniques used were wire spacing for power and routing priorities based on interconnect power. The lowering of wires capacitance enabled reduction of the size and power consumption of drivers. The power-aware router was tested with functional blocks of the processor analyzed, saving an average of 14% of the dynamic power (including the effect of drivers downsizing).
This thesis concludes that the interconnect power is the majority of the dynamic power, and interconnect power reduction techniques should be applied at all the design stages as it can reduce the majority of the interconnect power.