|M.Sc Thesis||Department of Electrical Engineering|
|Supervisor:||Assoc. Prof. Ginosar Ran|
An adaptive predictive clock synchronizer is presented . The adaptive predictive synchronizer takes advantage of the periodic nature of clocks in order to predict potential conflicts in advance. The synchronizer then uses this information to conditionally employ an input sampling delay to avoid such conflicts. The result is conflict-free synchronization with minimal latency. The adaptive predictive synchronizer adjusts automatically to a wide range of clock frequencies, regardless of whether the transmitter is faster or slower than the receiver. The synchronizer is also able to avoid sampling duplicate data or missing any inputs. The work also includes formal proof of correct operation of the synchronizer
The Adaptive Predictive Synchronizer comprises two parts, each one performing synchronization in one direction. The parts consist of an adaptive clock predictor, a clock selector, a “keep-out” control circuit, and a latching flip-flop. The synchronization algorithm can be proven mathematically.
The synchronizer contains a Duplicate and Miss Control, based on two edge triggered flip-flops. That control avoids duplicate sampling of the same data by a fast receiver, or missing any data by a slow receiver. Meta-stability of this control is eluded by using the delayed local clock instead of the regular clock.
The adaptive predictive synchronizer is compared to a two-flip-flop synchronizer and two types of FIFO synchronizer, a stream FIFO and a packet FIFO. The adaptive predictive synchronizer achieves minimum latency and maximum throughput of all the synchronizers.