|M.Sc Student||Guy Tamir|
|Department||Department of Electrical Engineering||Supervisor||Full Professor Ginosar Ran|
Synchronizing two asynchronous systems might cause degradation or even failure. Clock-data contention may cause a flop to either extend its propagation delay or enter metastability. In metastable state, the outputs assume voltage levels that do not represent legal digital values. Flip flops exit metastability after a random length of time. That delay may cause malfunction in the rest of the digital system. Metastability is characterized by MTBF (Mean Time Between Failures), which is affected by the settling time constant tau and the window of vulnerability Tw .
[Dike and Burton 1999] have shown how to find tau by simulation, but fail to handle skewed bi-stables. We show that how to simulate a wider range of metastability conditions. We also show how to compute Tw by simulations.
Factors that affect tau and Tw include the balance and size of capacitance of the two nodes of the latch, starting voltage difference, and sizes of the latch transistors.
A number of synchronizers are analyzed: The Jamb Latch, the Back Gate, the Inductive Input, and the Current Mirror synchronizer. Some novel circuits are proposed: The Second Chance, Delayed Clock, Tri Pull and Stairs synchronizers. They are all designed to shorten the time to exit of metastability.