|M.Sc Student||Tomer Morad|
|Subject||Data Trace Cache|
|Department||Department of Electrical Engineering||Supervisors||Professor Emeritus Weiser Uri|
|Professor Emeritus Kolodny Avinoam|
Multiple port instruction and data caches are required in order to achieve high performance on wide-issue superscalar microprocessors. However, the area and speed impact of implementing a full blown multiport cache is substantial. The highly predictable nature of the instruction stream has enabled trace caches to effectively fetch instructions from more than one cache block in each cycle. Our analysis shows that the data accesses stream also consists of recurring traces, hinting that a Data Trace Cache that exploits these recurring accesses is feasible.
An attempt to design a data trace cache that exploits recurring traces in the data access stream is shown. However, the proposed data trace cache architecture exhibits inferior performance compared to previous simple methods which aim at creating virtual multiport data caches. The main reason for this is the frequent data updates in the data cache compared to the infrequent self modifying code in instruction caches.
Overall, the simpler methods provide superior performance when compared to the proposed data trace cache architecture. In this work an analysis of the data access stream is presented. Four data access stream properties are identified: sequence repetition, spatial locality, temporal locality, and data forwarding. Then, simple architectures that exploit these data access stream properties are presented. An architecture for the data trace cache is proposed, and the reasons for its inferior results are explained.