|Ph.D Thesis||Department of Materials Science and Engineering|
|Supervisors:||Prof. Eizenberg Moshe|
|Prof. Kaplan Wayne D.|
The success of future gigascale integrated circuit chip technology depends critically upon the introduction of low dielectric constant (low-k) materials as interlayer dielectrics, and their integration with copper, the low resistivity interconnect metal of choice. Currently the interest is focused on porous silica-based films due to their ultra low-k and high compatibility to the current silica technology.
Nanoporous silica-based films were deposited by surfactant templated self-assembly spin-on deposition (SOD). Other types of low-k materials, with low density silica-based films were deposited by plasma enhanced chemical vapor deposition (PECVD), and CVD processes. The microstructure and chemical bonding of these low-k films were correlated with their dielectric properties. Different microstructural models were suggested for the SOD and CVD films, which were in agreement with known physical models.
The dielectric integrity of silica-based films was evaluated by characterizing metal-insulator-semiconductor (MIS) devices subjected to thermal and electric bias stresses. An interesting failure mechanism involving the degradation of the dielectric by copper ions was found for the different studied dielectrics subjected to bias thermal stresses. The mechanism of copper diffusion into porous silica based films was determined by analyzing the copper depth profile evolution with thermal anneals. A kinetic model based on mass conservation was suggested, and quantitative analysis showed that copper diffused in the dielectric film through the interconnected pore surfaces. A qualitative physical description for the morphological failure mechanism was suggested.